The present invention relates to a system and method for generating codes and, in particular, a system and method for generating pseudo-random or arbitrary codes using primarily memory and latch circuitry.
Code generators are used in many areas of electronics. The most common generators consist of a serial-input, parallel-output shift register with selected outputs being exclusive-or'd and fed back to the data input of the shift register. These codes are limited and only minimally arbitrary and provide no flexibility for selecting alternative codes or varying phases of one code. These drawbacks are exacerbated, since most of these circuits are hardwired.
As noted, most code generators of this type are restricted to a single code. A primary concern with code generators is avoiding loading all zeros in the code generator; thereby, causing the code generator to cease operation. These types of code generators are often used to generate maximal-length linear codes for direct sequence spread spectrum communication systems. They may be used to test communication lines and as building blocks in stream ciphers. These codes are typically equal to 2.sup.N-1, where N is equal to the number of shift registers. As an example, an 8 bit shift register is capable of generating one of 16 possible 255-bit codes. The code is a function of the selected feedback outputs.
Read-only memories (ROM's) have been used to store arbitrary codes and they are immune to situations resulting in the shift register having all zeros. Typically, the ROM is addressed by an address counter, which must be reset at the end of the code. Resetting this counter requires a means to determine that the end of the code has been reached and means to reset the address counter accordingly. Furthermore, a data latch is required to latch the data from the ROM to avoid an erroneous output due to settling after inputs to the address line are changed. Since most ROM's provide a parallel 8-bit wide data output and the required code is serial, most ROM-based code generators either output eight different codes simultaneously, which requires further logic to select the required code, or store eight bits of the code per byte, which requires circuitry adapted to load the eight bits into a parallel-input to serial-output shift register and clock the register contents serially. The latter configuration requires two clocks running at different frequencies. As is easily seen, such a circuit becomes very complex and expensive due to the large number of circuit elements.
Thus, there is a need for an inexpensive way to generate any required pseudo-random or arbitrary code. The means should avoid ceasing operation due to an all-zero condition in the shift registers and avoid requiring an address counter to access the code. Furthermore, there is a need for a means to generate and select multiple codes and/or different phases thereof in a simple and inexpensive manner.